1. Field of the Invention
Generally, the present disclosure relates to microstructure devices, such as integrated circuits, and, more particularly, to the metallization layers including highly conductive metals, such as copper, and dielectric materials including air gaps.
2. Description of the Related Art
In modern integrated circuits, minimum feature sizes, such as the channel length of field effect transistors, have reached the deep sub-micron range, thereby steadily increasing performance of these circuits in terms of speed and/or power consumption and/or diversity of circuit functions. As the size of the individual circuit elements is significantly reduced, thereby improving, for example, the switching speed of the transistor elements, the available floor space for interconnect lines electrically connecting the individual circuit elements is also decreased. Consequently, the dimensions of these interconnect lines and the spaces between the metal lines have to be reduced to compensate for a reduced amount of available floor space and for an increased number of circuit elements provided per unit area.
In integrated circuits having minimum dimensions of approximately 0.35 μm and less, a limiting factor of device performance is the signal propagation delay caused by the switching speed of the transistor elements. As the channel length of these transistor elements has now reached 50 nm and less, the signal propagation delay is no longer limited by the field effect transistors but is limited, owing to the increased circuit density, by the interconnect lines, since the line-to-line capacitance (C) is increased and also the resistance (R) of the lines is increased due to their reduced cross-sectional area. The parasitic RC time constants and the capacitive coupling between neighboring metal lines, therefore, require the introduction of a new type of material for forming the metallization layer.
Traditionally, metallization layers, i.e., the wiring layers including metal lines and vias for providing the electrical connection of the circuit elements according to a specified circuit layout, are formed by a dielectric layer stack including, for example, silicon dioxide and/or silicon nitride, with aluminum as the typical metal. Since aluminum suffers from significant electromigration at higher current densities that may be necessary in integrated circuits having extremely scaled feature sizes, aluminum is being replaced by, for instance, copper, which has a significantly lower electrical resistance and a higher resistivity against electromigration. For highly sophisticated applications, in addition to using copper and/or copper alloys, the well-established and well-known dielectric materials silicon dioxide (k≈4.2) and silicon nitride (k>7) may increasingly be replaced by so-called low-k dielectric materials having a relative permittivity of approximately 3.0 and less. However, the transition from the well-known and well-established aluminum/silicon dioxide metallization layer to a copper-based metallization layer possibly in combination with a low-k dielectric material is associated with a plurality of issues to be dealt with.
For example, copper may not be deposited in relatively high amounts in an efficient manner by well-established deposition methods, such as chemical and physical vapor deposition. Moreover, copper may not be efficiently patterned by well-established anisotropic etch processes. Therefore, the so-called damascene or inlaid technique is frequently employed in forming metallization layers including copper lines and vias. Typically, in the damascene technique, the dielectric layer is deposited and then patterned for receiving trenches and via openings that are subsequently filled with copper or alloys thereof by plating methods, such as electroplating or electroless plating. Moreover, since copper readily diffuses in a plurality of dielectrics, such as silicon dioxide and in many low-k dielectrics, the formation of a diffusion barrier layer at interfaces with the neighboring dielectric material may be required. Moreover, the diffusion of moisture and oxygen into the copper-based metal has to be suppressed as copper readily reacts to form oxidized portions, thereby possibly deteriorating the characteristics of the copper-based metal line with respect to adhesion, conductivity and the resistance against electromigration.
During the filling in of a conductive material, such as copper, into the trenches and via openings, a significant degree of overfill has to be provided in order to reliably fill the corresponding openings from bottom to top without voids and other deposition-related irregularities. Consequently, after the metal deposition process, excess material may have to be removed and the resulting surface topography is to be planarized, for instance, by using electrochemical etch techniques, chemical mechanical polishing (CMP) and the like. For example, during CMP processes, a significant degree of mechanical stress may be applied to the metallization levels formed so far, which may cause structural damage to a certain degree, in particular when sophisticated dielectric materials of reduced permittivity are used. As previously explained, the capacitive coupling between neighboring metal lines may have a significant influence on the overall performance of the semiconductor device, in particular in metallization levels, which are substantially “capacitance driven,” i.e., in which a plurality of closely spaced metal lines have to be provided in accordance with device requirements, thereby possibly causing signal propagation delay and signal interference between neighboring metal lines. For this reason, so-called low-k dielectric materials or ultra low-k materials may be used, which may provide a dielectric constant of 3.0 and significantly less in order to enhance the overall electrical performance of the metallization levels. On the other hand, typically, a reduced permittivity of the dielectric material is associated with a reduced mechanical stability, which may require sophisticated patterning regimes so as to not unduly deteriorate reliability of the metallization system.
The continuous reduction of the feature sizes, however, with gate lengths of approximately 40 nm and less, may demand for even more reduced dielectric constants of the corresponding dielectric materials, which may increasingly contribute to yield loss due to, for instance, insufficient mechanical stability of respective ultra low-k materials. For this reason, it has been proposed to introduce “air gaps,” at least at critical device areas, since air or similar gases may have a dielectric constant of approximately 1.0, thereby providing reduced overall permittivity, while nevertheless allowing the usage of less critical dielectric materials. Hence, by introducing appropriately positioned air gaps, the overall permittivity may be reduced while, nevertheless, the mechanical stability of the dielectric material may be superior compared to conventional ultra low-k dielectrics. For example, it has been proposed to introduce nano holes into appropriate dielectric materials, which may be randomly distributed in the dielectric material so as to significantly reduce the density of the dielectric material. However, the creation and distribution of the respective nano holes may require a plurality of sophisticated process steps for creating the holes with a desired density, while at the same time the overall characteristics of the dielectric material may be changed in view of the further processing, for instance with respect to planarizing surface areas, depositing further materials and the like.
In other approaches, advanced lithography processes are additionally introduced so as to create appropriate etch masks for forming gaps near respective metal lines with a position and size as defined by the lithographically formed etch mask. In this case, however, additional cost intensive lithography steps may be required, wherein also the positioning and the dimensioning of the corresponding air gaps may be restricted by the capabilities of the respective lithography processes. Since, typically, in critical metallization levels, the lateral dimensions of metal lines and the spacing between adjacent metal lines may be defined by critical lithography steps, an appropriate and reliable manufacturing sequence for providing intermediate air gaps may be difficult to be achieved on the basis of the available lithography techniques.
In other conventional approaches, the dielectric material of the metallization layer under consideration may be etched selectively with respect to the metal lines down to a specified depth, thereby avoiding complex lithography steps for positioning the air gaps between the metal lines. Consequently, a self-aligned technique may be accomplished by using the etch selectivity between the metal lines and the low-k dielectric material. In other cases, at least a portion of the dielectric material may be formed by using an appropriate material composition, which may allow an efficient removal, for instance, on the basis of well-established etch recipes and the like. In this case, the metal lines may be formed in the sacrificial dielectric material which may then be efficiently removed so as to obtain corresponding recesses, which may subsequently be capped by depositing a dielectric material. Consequently, the latter approaches may provide self-aligned process strategies by removing at least a portion of the dielectric material down to a specified depth on the basis of etch techniques without requiring critical lithography processes. Although these approaches are very promising and may result in a cost-efficient production sequence, there are still significant drawbacks associated with the patterning of vias and the trenches in the layer stack comprising the low-k material and the sacrificial material, in particular for device generations including transistors of critical dimensions of approximately 40 nm and less.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.